Snooping protocol proposal to Improve Cache Performance via Reducing Memory Access Time

Abstract

Cache design in multiprocessor systems usually involves maintaining data consistency between these processors that are achieved through implementation one of most important protocols used for this purpose which are snooping protocol and directory-based protocol. It also includes improved memory access time by reducing the time spent in three cases which are: miss rate, miss penalty and time to hit in the cache. Generally, there exist three critical attributes that have an impact on the performance of any coherence protocol in the cache which are low-latency cache-to-cache misses, bandwidths efficiency and scalability challenges. In this research, a new protocol has been proposed for coherent caches named PMOESI protocol. This protocol has the same states of a standard MOESI protocol but the difference is in adding a new state named Premier "P" and also an exclusive reference buffer is designed to be added to Level1 cache. The MOESI protocol is a version of the snooping coherence protocol which each block in the cache memory can have one of five (Modified, Owned, Exclusive, Shared, Invalid) states. From using the proposed protocol, the performance is enhanced as a result of reducing latency time in comparison with MOESI protocol. The reason behind this improvement is in using low latency cache to cache transfer to deliver the desired block instead of fetching this block from main memory for responding to request writing of remote processors.